{"id":12531,"date":"2024-12-18T21:26:57","date_gmt":"2024-12-18T21:26:57","guid":{"rendered":"https:\/\/www.tun.com\/home\/?p=12531"},"modified":"2024-12-18T21:26:58","modified_gmt":"2024-12-18T21:26:58","slug":"mit-engineers-develop-groundbreaking-high-rise-3d-chips","status":"publish","type":"post","link":"https:\/\/www.tun.com\/home\/mit-engineers-develop-groundbreaking-high-rise-3d-chips\/","title":{"rendered":"MIT Engineers Develop Groundbreaking &#8216;High-Rise&#8217; 3D Chips"},"content":{"rendered":"\n<div class=\"wp-block-group\"><div class=\"wp-block-group__inner-container is-layout-constrained wp-block-group-is-layout-constrained\">\n<div class=\"wp-block-uagb-blockquote uagb-block-e7eb3fc3 uagb-blockquote__skin-border uagb-blockquote__stack-img-none\"><blockquote class=\"uagb-blockquote\"><div class=\"uagb-blockquote__content\">MIT engineers have innovated a novel method to fabricate sturdy 3D chips without the need for bulky silicon wafers. This advancement promises to significantly enhance computing power, fueling next-generation AI, memory and logic devices.<\/div><footer><div class=\"uagb-blockquote__author-wrap uagb-blockquote__author-at-left\"><\/div><\/footer><\/blockquote><\/div>\n\n\n\n<div class=\"wp-block-group is-content-justification-space-between is-nowrap is-layout-flex wp-container-core-group-is-layout-0dfbf163 wp-block-group-is-layout-flex\"><div style=\"font-size:16px;\" class=\"has-text-align-left wp-block-post-author\"><div class=\"wp-block-post-author__content\"><p class=\"wp-block-post-author__name\">The University Network<\/p><\/div><\/div>\n\n\n<div class=\"wp-block-uagb-social-share uagb-social-share__outer-wrap uagb-social-share__layout-horizontal uagb-block-ee584a31\">\n<div class=\"wp-block-uagb-social-share-child uagb-ss-repeater uagb-ss__wrapper uagb-block-ec619ce7\"><span class=\"uagb-ss__link\" data-href=\"https:\/\/www.facebook.com\/sharer.php?u=\" tabindex=\"0\" role=\"button\" aria-label=\"facebook\"><span class=\"uagb-ss__source-wrap\"><span class=\"uagb-ss__source-icon\"><svg xmlns=\"https:\/\/www.w3.org\/2000\/svg\" viewBox=\"0 0 512 512\"><path d=\"M504 256C504 119 393 8 256 8S8 119 8 256c0 123.8 90.69 226.4 209.3 245V327.7h-63V256h63v-54.64c0-62.15 37-96.48 93.67-96.48 27.14 0 55.52 4.84 55.52 4.84v61h-31.28c-30.8 0-40.41 19.12-40.41 38.73V256h68.78l-11 71.69h-57.78V501C413.3 482.4 504 379.8 504 256z\"><\/path><\/svg><\/span><\/span><\/span><\/div>\n\n\n\n<div class=\"wp-block-uagb-social-share-child uagb-ss-repeater uagb-ss__wrapper uagb-block-32d99934\"><span class=\"uagb-ss__link\" data-href=\"https:\/\/twitter.com\/share?url=\" tabindex=\"0\" role=\"button\" aria-label=\"twitter\"><span class=\"uagb-ss__source-wrap\"><span class=\"uagb-ss__source-icon\"><svg xmlns=\"https:\/\/www.w3.org\/2000\/svg\" viewBox=\"0 0 512 512\"><path d=\"M389.2 48h70.6L305.6 224.2 487 464H345L233.7 318.6 106.5 464H35.8L200.7 275.5 26.8 48H172.4L272.9 180.9 389.2 48zM364.4 421.8h39.1L151.1 88h-42L364.4 421.8z\"><\/path><\/svg><\/span><\/span><\/span><\/div>\n\n\n\n<div class=\"wp-block-uagb-social-share-child uagb-ss-repeater uagb-ss__wrapper uagb-block-1d136f14\"><span class=\"uagb-ss__link\" data-href=\"https:\/\/www.linkedin.com\/shareArticle?url=\" tabindex=\"0\" role=\"button\" aria-label=\"linkedin\"><span class=\"uagb-ss__source-wrap\"><span class=\"uagb-ss__source-icon\"><svg xmlns=\"https:\/\/www.w3.org\/2000\/svg\" viewBox=\"0 0 448 512\"><path d=\"M416 32H31.9C14.3 32 0 46.5 0 64.3v383.4C0 465.5 14.3 480 31.9 480H416c17.6 0 32-14.5 32-32.3V64.3c0-17.8-14.4-32.3-32-32.3zM135.4 416H69V202.2h66.5V416zm-33.2-243c-21.3 0-38.5-17.3-38.5-38.5S80.9 96 102.2 96c21.2 0 38.5 17.3 38.5 38.5 0 21.3-17.2 38.5-38.5 38.5zm282.1 243h-66.4V312c0-24.8-.5-56.7-34.5-56.7-34.6 0-39.9 27-39.9 54.9V416h-66.4V202.2h63.7v29.2h.9c8.9-16.8 30.6-34.5 62.9-34.5 67.2 0 79.7 44.3 79.7 101.9V416z\"><\/path><\/svg><\/span><\/span><\/span><\/div>\n<\/div>\n<\/div>\n<\/div><\/div>\n\n\n\n<p>In an industry-defining breakthrough, MIT engineers have unveiled a groundbreaking new approach to semiconductor design. By developing a novel method to construct high-rise, multilayered 3D chips without the need for traditional silicon wafer substrates, this innovation could radically amplify the efficiency and capability of future electronic devices.<\/p>\n\n\n\n<p>Traditionally, the number of transistors on a chip has increased by making them smaller and packing them tightly on a single surface. But as physical and technological limits are reached, the industry is turning to vertical stacking \u2014 envisioning chips much like high-rise buildings instead of sprawling ranch houses. These multi-layer chips have the potential to exponentially increase data handling and processing capabilities.<\/p>\n\n\n\n<p>Jeehwan Kim, a study author and an associate professor of mechanical engineering at MIT, calls this breakthrough a game changer. <\/p>\n\n\n\n<p>\u201cThis breakthrough opens up enormous potential for the semiconductor industry, allowing chips to be stacked without traditional limitations,\u201d he said in a <a href=\"https:\/\/news.mit.edu\/2024\/mit-engineers-grow-high-rise-3d-chips-1218\" title=\"\">news release<\/a>. \u201cThis could lead to orders-of-magnitude improvements in computing power for applications in AI, logic, and memory.\u201d<\/p>\n\n\n\n<p><a href=\"https:\/\/www.nature.com\/articles\/s41586-024-08236-9\" target=\"_blank\" rel=\"noopener\" title=\"\">Published<\/a> in the journal Nature, the study details how this approach was realized. <\/p>\n\n\n\n<p>The MIT team, in collaboration with Samsung Advanced Institute of Technology, Sungkyunkwan University in South Korea and the University of Texas at Dallas, successfully fabricated these multilayered chips using high-quality semiconducting materials stacked directly on top of one another. Their method circumvents the need for thick, bulky silicon wafers, making room for more direct and efficient communication between layers.<\/p>\n\n\n\n<div style=\"height:21px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n<div class=\"wp-block-image\">\n<figure class=\"aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"900\" height=\"600\" src=\"https:\/\/www.tun.com\/home\/wp-content\/uploads\/2024\/12\/MIT-high-rise-3D-chips.jpg\" alt=\"\" class=\"wp-image-12612\" srcset=\"https:\/\/www.tun.com\/home\/wp-content\/uploads\/2024\/12\/MIT-high-rise-3D-chips.jpg 900w, https:\/\/www.tun.com\/home\/wp-content\/uploads\/2024\/12\/MIT-high-rise-3D-chips-300x200.jpg 300w, https:\/\/www.tun.com\/home\/wp-content\/uploads\/2024\/12\/MIT-high-rise-3D-chips-768x512.jpg 768w\" sizes=\"auto, (max-width: 900px) 100vw, 900px\" \/><\/figure>\n<\/div>\n\n\n<p class=\"has-text-align-center\"><em>Credit:<\/em> Cube 3D Graphic<\/p>\n\n\n\n<div style=\"height:7px\" aria-hidden=\"true\" class=\"wp-block-spacer\"><\/div>\n\n\n\n<p>Kim\u2019s team had previously achieved significant progress in growing high-quality semiconducting materials on amorphous surfaces, which are part of the diverse topography of completed chips. These materials, known as transition-metal dichalcogenides (TMDs), maintain their properties even at atomic-scale dimensions, unlike silicon, whose performance degrades significantly at smaller scales.<\/p>\n\n\n\n<p>In earlier experiments, the team grew TMDs on silicon wafers with tiny, pattern-creating pockets. These pockets served as \u201cseeds\u201d where atoms settled and grew in a single-crystalline pattern. The challenge, however, was doing so at high temperatures which would damage the underlying circuitry. <\/p>\n\n\n\n<p>\u201cYou have to grow this single-crystalline material below 400 Celsius; otherwise, the underlying circuitry is completely cooked and ruined,\u201d Kim added.<\/p>\n\n\n\n<p>To overcome this, the team adapted a concept from metallurgy. They discovered that nucleation \u2014 the initial phase of crystal formation \u2014 occurs more effectively at the mold\u2019s edges, a process which requires less energy and lower temperatures. Leveraging this concept, they placed TMD seeds at the edges of the pockets, facilitating the growth of single-crystalline material at a much lower 380 degrees Celsius.<\/p>\n\n\n\n<p>The breakthrough didn\u2019t stop there. The researchers also successfully stacked alternating layers of different TMDs (molybdenum disulfide for n-type transistors, and tungsten diselenide for p-type transistors) on top of each other directly. <\/p>\n\n\n\n<p>This method effectively doubles the density of a chip\u2019s semiconducting elements, greatly enhancing its computational prowess. <\/p>\n\n\n\n<p>\u201cA product realized by our technique is not only a 3D logic chip but also 3D memory and their combinations,\u201d Kim added.<\/p>\n\n\n\n<p><span style=\"font-weight: 400;\">First author Kiseok Kim, a postdoctoral associate in Jeehwan Kim<\/span>&#8216;s lab,<span style=\"font-weight: 400;\"> emphasizes the advantages over traditional 3D chips with silicon wafers.<\/span><\/p>\n\n\n\n<p><span style=\"font-weight: 400;\">\u201cConventional 3D chips have been fabricated with silicon wafers in-between, by drilling holes through the wafer \u2014 a process which limits the number of stacked layers, vertical alignment resolution, and yields,&#8221; he said in the news release. &#8220;Our growth-based method addresses all of those issues at once.\u201d<\/span><\/p>\n\n\n\n<p><span style=\"font-weight: 400;\">Jeehwan Kim recently founded FS2 (Future Semiconductor 2D materials) to commercialize this innovative approach. <\/span><\/p>\n\n\n\n<p><span style=\"font-weight: 400;\">\u201cWe so far show a concept at a small-scale device arrays. The next step is scaling up to show professional AI chip operation,\u201d he added.<\/span><\/p>\n\n\n\n<p><span style=\"font-weight: 400;\">Supported by the Samsung Advanced Institute of Technology and the Air Force Office of Scientific Research, this breakthrough by MIT pioneers sets the stage for the development of AI hardware that rivals today\u2019s supercomputers, integrated into everyday devices from laptops to wearables.<\/span><\/p>\n\n\n\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>In an industry-defining breakthrough, MIT engineers have unveiled a groundbreaking new approach to semiconductor design. By developing a novel method to construct high-rise, multilayered 3D chips without the need for traditional silicon wafer substrates, this innovation could radically amplify the efficiency and capability of future electronic devices. Traditionally, the number of transistors on a chip [&hellip;]<\/p>\n","protected":false},"author":3,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"single-no-separators","format":"standard","meta":{"_acf_changed":false,"_uag_custom_page_level_css":"","_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"footnotes":""},"categories":[17],"tags":[],"class_list":["post-12531","post","type-post","status-publish","format-standard","hentry","category-tech"],"acf":[],"aioseo_notices":[],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false},"uagb_author_info":{"display_name":"The University Network","author_link":"https:\/\/www.tun.com\/home\/author\/funky_junkie\/"},"uagb_comment_info":0,"uagb_excerpt":"In an industry-defining breakthrough, MIT engineers have unveiled a groundbreaking new approach to semiconductor design. By developing a novel method to construct high-rise, multilayered 3D chips without the need for traditional silicon wafer substrates, this innovation could radically amplify the efficiency and capability of future electronic devices. Traditionally, the number of transistors on a chip&hellip;","_links":{"self":[{"href":"https:\/\/www.tun.com\/home\/wp-json\/wp\/v2\/posts\/12531","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.tun.com\/home\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.tun.com\/home\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.tun.com\/home\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/www.tun.com\/home\/wp-json\/wp\/v2\/comments?post=12531"}],"version-history":[{"count":12,"href":"https:\/\/www.tun.com\/home\/wp-json\/wp\/v2\/posts\/12531\/revisions"}],"predecessor-version":[{"id":12614,"href":"https:\/\/www.tun.com\/home\/wp-json\/wp\/v2\/posts\/12531\/revisions\/12614"}],"wp:attachment":[{"href":"https:\/\/www.tun.com\/home\/wp-json\/wp\/v2\/media?parent=12531"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.tun.com\/home\/wp-json\/wp\/v2\/categories?post=12531"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.tun.com\/home\/wp-json\/wp\/v2\/tags?post=12531"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}